Hands-on Workshops for Statistical Mode of Channel Simulator … and More!

(Syndicated content from: http://signal-integrity-tips.com/2009/ands-on-workshops-statistical-mode-channel-simulator/)

We’re offering five complementary signal integrity hands-on workshops entitled “Design Using Fast Channel Simulation and Statistical Eye Diagrams.” Seating is limited for this complimentary event. Early enrollment is advised.

Why this workshop is important

Signal integrity engineers need to determine ultralow BER contours for thousands of points in the design space in order to select the optimum set of characteristics for transmitter, channel, and receiver. Traditional techniques consume a prohibitively long simulation time. For this reason we’ve implemented a new statistical mode in our Channel Simulator that eliminates the need for long, multi-million-bit simulations. Now you can generate eye diagrams with ultralow BER contours in just a few seconds.

This in-depth hands-on workshop will demonstrate the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables, and will also cover tools and modes that can be used in exceptional cases (e.g. equalizer adaptation, non-linearity, or specific bit patterns) where statistical eye techniques cannot be applied.

You will get first hand experiencing using signal integrity features that are new in ADS 2009 Update 1 and EMPro 2009, including equalizers, DDR compliance toolkit, and via simulation with 3DEM.

Who should attend this workshop

Signal integrity engineers for multigigabit links who are running into effects previously only seen in RF and microwave circuits.

Dates & Locations

September 15, 2009 – Ottawa, ON
September 22, 2009 – Chelmsford, MA
September 24, 2009 – Minneapolis, MN
September 29, 2009 – Santa Clara, CA
October 1, 2009 – Anaheim, CA

Agenda

All times are local
9:30a.m. – Register/Breakfast
10:00a.m. – Hands-on workshop part 1

• ADS for signal integrity analysis
• HSPICE netlist including W-element in ADS
• Modeling and simulation of a PCI Express Gen2 channel using Channel Simulator in:
• Bit by bit mode
• Statistical mode
• Equalizer, LMS, RLS, and ZF, and equalizer tap coefficient calculation

12:00p.m. – Lunch
1:00p.m. – Workshop part 2

• Channel optimization for eye diagram and BER
• HDMI transmitter and how it can be modeled in ADS
• DDR Compliance Toolkit
• 3DEM simulation of a via model with EMPro

3:00p.m. – End

S-parameters

(Syndicated content from: http://signal-integrity-tips.com/2009/s-parameters/)

Although scattering parameters (S-parameters) have been used by RF and microwave engineers for over 40 years, their adoption still isn’t universal in the signal integrity field. With this informal poll I’m hoping to understand what the barriers (if any) are.

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In case I’ve peaked your interest, here are an application note and a seminar presentation on network analysis with S-parameters. They aren’t specific to signal integrity, but are nevertheless very useful in signal integrity engineering:

• "Network Analyzer Basics", slides and comprehensive speaker notes from our “Back to Basics” seminar series. Slides 27-29 have an good introductin to S-parameters.
• "S-Parameter Techniques for Faster, More Accurate Network Design", an update of the classic Application Note AN 95-1, Agilent Technologies, PDF slides plus interactive features. Or download a scan of Richard W. Anderson’s original AN 95-1 S-parameter application note.

Web 2.0 Democratization of First Journalism, Now Conferences?

(Syndicated content from: http://signal-integrity-tips.com/2009/web-2-0-democratization-first-journalism-now-conferences/)

The web has democratized journalism by lowering the entry barrier to publishing. Now it seems it’s democratizing conferences: just ask a company to donate its cafeteria or auditorium space for an evening, post some notices on the internet, ask people to bring themselves, their ideas, some sandwiches and soda, and — voilà — instant conference! Start of a trend? Compare the two weeks’ lead time and near zero cost of the announcement below and the 9-month lead time and million dollar budget for, say, DesignCon. Anyway, good luck and power to the people!

Here is Vikash Rungta’s announcement in full.

Folks,

1st event FPGACamp is coming up on Aug’26 at Silicon Valley, CA. The topic of the event is “High Speed Serial Interfaces – Protocols, IPs & Devices”. The event is going to be vendor neutral & technical.

I am here looking for speakers / recommendation for speakers. We would like to have a segment about : what FPGA designers & board designers should know to minimize the SI risk including termination, layout guidelines, power supply & lab bringup (may be list few challenges in bring-up, and tools to debug).

We certainly would like to stay vendor neutral, so we need someone who is not part of one of the vendors.

The admission & booths are completely FREE, so rest of the folks interested in attending/ setting up a booth RSVP at FPGACamp or LinkedIn Events: FPGA Camp High Speed Serial Interfaces

Event Details

The idea behind FPGA Camp is to bring engineers together and discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories.

We are hoping that this would act as a platform to bring all the FPGA users together more often.

Agenda

5:30 – 6:00: Registration and demo
6:00 – 7:00 : Tech Talk- “High Speed Serial Interface: Protocols, IPs & Devices”
7:00 – 7:30 : Vendor talk- a brief talks from the vendors offering High Speed Serial Interface devices or IPs. (5 to 10 Mns each).
7:30 – 8:00 : Networking and exhibits

High Speed Serial Interface: Protocols, IPs & Devices

Recent expansion in the video usage and growth in the Internet use have created a demand to move more data faster than ever. To meet this demand, system & chip designers are moving towards high speed serial interfaces such as PCIe, XAUI, Interlaken, XFI, 10GbE etc. With FPGA devices currently supporting speeds upto ~12.5Gb per IO pair, which makes FPGAs a unique choice for the next design.

This talk will focus on familiarizing people with various protocols (both currently used & emerging), IPs & Devices which can be used to solve the next system problem.

The talk will be followed by quick presentations from some of the vendors offering these solutions (no marketing talk, only technical).

Thanks,
Vikash

ADS 2009 Update 1 – What’s New

(Syndicated content from: http://signal-integrity-tips.com/2009/ads-2009-update-1-whats-new/)
Here’s a 10-minute video clip about the new statistical mode for Channel Simulator. It does the work of more than 40-hours of transient (SPICE-like) simulation in 40 seconds!.

PDF of slides with speaker notes

Right click to download MP4 for your iPod or media player

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)

My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.

Plan to attend another conference? Please leave a comment below.

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