Meet Us IRL (In Real Life) at DesignCon 2009

(Syndicated content from http://signal-integrity-tips.com/2009/meet-us-irl-in-real-life-at-designcon-2009/)

Despite rumors from some Web 2.0 fanatics that it isn’t necessary, you can still actually meet people “IRL” (in real life) not just virtually via the web. My Agilent colleagues and I will be staffing Booth #305 at DesignCon 2009, in Santa Clara CA, Feb 2-5 2009. Stop by and say hello!

PS: My entry to the DesignCon® 2009 Video Contest is entitled “Day in the Life of an Agilent EEsof EDA Chiphead®”. Is there really an upcoming ISO 1984 standard? Find out in this (hopefully) hilarious parody of a famous series of YouTube videos.

PPS: Here are the Agilent papers and panels. Example: “7-TA2″ means track 7, Tuesday AM, paper 2.

• 7-TA2: “Practical Analysis of Backplane Vias for 5 Gbps and Above”, Eric Bogatin, Sanjeev Gupta (EEsof), Mike Resso (CTD)
• 8-TA1: “The use of Optimization in Signal Integrity performance Centric High Speed Digital Design Flows”, Brahim Bensalem (Intel), Sanjeev Gupta (EEsof)
• 8-TA3: “Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Test”, Ransom Stephens, Marcus Mueller (DTD_DPT)
• 13-TA4: “Verify your signal integrity margins: De-embedding of fixtures and probing in a real time digital oscilloscope”, Jim Choate (DTD_Scopes)
• 12-WA2: “VNA Characterization of Cable Assemblies for Supercomputer Applications”, Greg Edlund (IBM), Mike Resso (CTD)
• 12-WA3: “Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments”, Julian Ferry (Samtec), Mike Resso (CTD), OJ Danzy (CTD)
• 7-WA4: “BER Performances for High-Speed Serial Link System Estimated by using Quasi-Analytical Method”, Ding-qing Lu (EEsof)
• 12-THA2: “A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels”, Weiping Hou (Huawei), Quan-Li Li (Agilent China)
• TF-MA4: “Fixturing and Calibration Techniques for Obtaining Wide Bandwidth Measured Data for Time Domain Simulations and Measurement-Based Modeling”, Heidi Barnes (Verigy), Sanjeev Gupta (EEsof), Mike Resso (CTD)
• TP-MP: “The case of the closing eye – Addressing the Industry’s Next Gen Serial Data Design Validation Challenges”, Chris Loberg (Tek), Karl Kachigan (DTD)
• TP-WP: “Do it right or do it over? Signal integrity engineer in the era of highly compressed project schedules”, Colin Warwick (EEsof)

Open the Eye Solution – Mark Broman

(Syndicated content from http://signal-integrity-tips.com/2009/open-the-eye-solution-mark-broman/)
Mark Broman of Thin Film Technology Corp submitted this solution to our puzzle contest. Mark writes:

This puzzle appears to be a classic lossy ISI problem. We work with these all the time. So much so that we developed a line of high pass filters that are the inverse function of the typical bessel loss of a transmission line. We plot the S-parameters and mark the loss point of the fundamental frequency of the expected data rate. We then use a measured model of this filter part with the channel measurement to show the expected eye using this filter.

ADS schematics and resulting eye diagram

This is very easy and took about 3 minutes, 10 minutes tops if you count installing the model library. This is not the tightest solution but is still very effective and the simulation is done from measured models on both ends. Our experience is that 10db channel loss budget are pretty standard but this one is 15dB. The simulated TDR of the trace shows an impedance discontinuity that is most likely a via stub that pushes the loss down and out of budget.